1. Field of the Invention
The present invention relates to a display device and a method for driving a display device, and is applicable to active matrix display devices made up of organic electroluminescent (OEL) elements. More particularly, the present invention compensates for fluctuations in the mobility of a drive transistor by successively setting the voltage of a signal line to an intermediate voltage and to a tone voltage. Moreover, this intermediate voltage is varied in accordance with both the tone voltage as well as the distance from the input terminal of the write signal to a respective pixel. In so doing, fluctuations in the mobility of the drive transistor are appropriately compensated for, and shading due to irregularities in the waveform of the write signal is prevented.
2. Description of the Related Art
In the active matrix display devices utilizing OEL elements of the related art, a display unit is formed by disposing pixels in a matrix formation, each pixel including an OEL element and a drive circuit that drives the OEL element. The operation of each pixel is controlled by horizontal and vertical drive circuits disposed in the vicinity of the display unit, and thereby a desired image is displayed.
Japanese Unexamined Patent Application Publication No. JP 2006-227237 proposes technology related to OEL-based display devices, wherein a tone is set for each pixel to compensate for fluctuations in the threshold voltage of the drive transistor that drives the OEL elements. In so doing, reduced image quality due to fluctuations in the threshold voltage is prevented and high image quality is ensured, even in the case where an N-channel transistor is used.
However, there is a disadvantage in that the drive transistor adopted in these types of display devices exhibits fluctuations not only in the threshold voltage, but also in mobility. Thus these types of display devices are problematic in that image quality is also reduced as a result of fluctuations in the mobility of the drive transistor.
One method of resolving this problem has been devised wherein the circuit for each pixel is configured as shown in FIG. 5. In the display device 1 shown in FIG. 5 herein, a display unit is formed by disposing a plurality of pixels 3 in a matrix formation. In each pixel 3, one terminal of a hold capacitor C1 for retaining the signal level is connected to the anode of an OEL element 4, while the other terminal of the signal level hold capacitor C1 is connected to a signal line SIG via an interposed write transistor TR1 that switches on/off according to a write signal WS. In each pixel 3, both terminals of the signal level hold capacitor C1 are connected to the source and gate of a drive transistor TR2, the drain of this drive transistor TR2 being connected to a scan line SCN that supplies power. In FIG. 5, Vcath is the cathode voltage of the OEL element 4, while Csub is an auxiliary capacitor disposed parallel to the OEL element 4.
In the display device 1, a write signal WS and a drive signal DS for supplying power are output to the scan line SCN by a write scan circuit (WSCN) 5A and a drive scan circuit (DSCN) 5B, respectively. In addition, a drive signal Ssig is output to the signal line SIG by the horizontal selector (HSEL) 6A of a horizontal drive circuit 6. The operation of the pixel 3 is controlled by the above.
FIG. 6 is a timing chart showing the operation of the pixel 3. The write transistor TR1 is switched on by raising the write signal WS (line (A) in FIG. 6) for a predetermined timing during a non-emitting period wherein light emission from the pixel 3 is suspended. In addition, during this non-emitting period of the pixel 3, the drive signal DS for supplying power (line (B) in FIG. 6) is lowered from a power supply voltage Vcc to a predetermined, fixed voltage Vini for a predetermined period starting from the commencement of the non-emitting period. In addition, the drive signal Ssig (line (C) in FIG. 6) is repeatedly alternated between the tone voltage Vsig of each pixel connected to the signal line SIG and a predetermined, fixed voltage Vofs. The tone voltage Vsig referred to herein is a voltage that indicates the luminance of the OEL element 4 provided in each pixel 3.
During the emitting period of the pixel 3 (i.e., the period wherein the OEL element 4 is made to emit light), the write transistor TR1 is switched off by the write signal WS, and the power supply voltage Vcc is supplied to the drive transistor TR2 by the drive signal DS. In so doing, the gate voltage Vg and the source voltage Vs of the drive transistor TR2 (lines (D) and (E) in FIG. 6) are stored on either terminal of the signal level hold capacitor C1. The OEL element 4 is then driven by the driving current Ids that arises due to the differential voltage between the terminals of the signal level hold capacitor C1. This driving current Ids is expressed by the equation below. The quantity Vgs referred to herein is the voltage between the gate and the source of the drive transistor TR2, and is equivalent to the differential voltage between the two terminals of the signal level hold capacitor C1. In addition, the quantity μ herein is the mobility, W is the channel width, L is the channel length, Cox is the capacitance of the gate insulator per unit area, and Vth is the threshold voltage, all with respect to the transistor TR2.
                    Equation        ⁢                                  ⁢        1                                                                      I          ds                =                              1            2                    ⁢          μ          ⁢                      W            L                    ⁢                                                    C                ox                            ⁡                              (                                                      V                    gs                                    -                                      V                    th                                                  )                                      2                                              (        1        )            
When the emitting period of the pixel 3 ends at a time t1, the drain voltage of the transistor TR2 is lowered to the predetermined voltage Vini by the drive signal DS for supplying power. The voltage Vini referred to herein is a voltage sufficiently low to cause the drain of the drive transistor TR2 to function as the source. This causes the accumulated charge at the terminal of the hold capacitor C1 on the side of the OEL element 4 to be discharged and carried to the scan line SCN via the drive transistor TR2. The source voltage Vs of the drive transistor TR2 is thereby lowered to the voltage Vini, and emission from the OEL element 4 in the pixel 3 ceases.
Subsequently, the voltage of the signal line SIG is lowered to a predetermined, fixed voltage Vofs by the drive signal Ssig at a time t2, and the write transistor TR1 is switched on by the write signal WS (lines (A) and (C) in FIG. 6). In so doing, the gate voltage Vg of the drive transistor TR2 in the pixel 3 is set to the voltage Vofs of the signal line SIG, and thus the voltage Vgs between the gate and the source of the drive transistor TR2 becomes Vofs-Vini. By thus setting the fixed voltages Vofs and Vini in the pixel 3, the expression Vofs-Vini yields a voltage that is larger than the threshold voltage Vth of the drive transistor TR2.
Subsequently, the drain voltage of the drive transistor TR2 in the pixel 3 is raised to the power supply voltage Vcc by the drive signal DS for supplying power at a time t3 (lines (A) to (C) in FIG. 6). This causes a charging current to flow from the power supply voltage Vcc to the terminal of the capacitor C1 on the side of the OEL element 4 via the drive transistor TR2, and as a result, the voltage Vs of the capacitor terminal on the side of the OEL element 4 gradually rises. While this also causes an influx of current to the OEL element 4 in the pixel 3, this influx of current is used to charge the capacitor of the OEL element 4 and the auxiliary capacitor Csub. Thus the OEL element 4 does not emit light at this point, and only the source voltage Vs of the drive transistor TR2 rises.
At a subsequent time t4, the write transistor TR1 of the pixel 3 is switched off by the write signal WS, and then the signal level of the signal line SIG is set to the tone voltage Vsig for the next corresponding pixel on the adjacent line. This causes the source voltage Vs of the drive transistor TR2 to gradually rise in accordance with the differential voltage between the terminals of the signal level hold capacitor at time t4. Moreover, the gate voltage Vg of the drive transistor TR2 also increases in conjunction with the increase in the source voltage Vs. Meanwhile, during this time the tone settings for the next corresponding pixel on the adjacent line are used to set the tone voltage Vsig of the signal line SIG.
After a fixed period of time has elapsed, the signal level of the signal line SIG is again switched to the voltage Vofs at a time t5, while additionally the write transistor TR1 is switched on by raising the write signal WS. When the differential voltage between the terminals of the signal level hold capacitor C1 in pixel 3 is greater than the threshold voltage of the drive transistor TR2, the above causes a charging current to flow from the power supply Vcc to the terminal of the signal level hold capacitor C1 on the side of the OEL element 4 via the drive transistor TR2, while at the same time maintaining the voltage Vofs at the signal level hold capacitor C1 on the side of the signal line SIG. As a result, the source voltage Vs of the drive transistor TR2 gradually rises. Moreover, when this increase in the source voltage Vs causes the voltage differential between the terminals of the signal level hold capacitor C1 to reach the threshold voltage Vth of the drive transistor TR2, the influx of charging current via the drive transistor TR2 ceases, and thus the increase in the source voltage Vs of the drive transistor TR2 also ceases.
After a fixed period of time has elapsed, the write transistor TR1 is switched off by the write signal WS at a time t6. In conducting this series of operations in the pixel 3, the period from the time t1 to the time t2 is assigned as the preliminary period for compensating for fluctuations in the threshold voltage Vth of the drive transistor TR2, wherein the voltage differential between the terminals of the signal level hold capacitor C1 is set to a voltage value that is larger than the threshold voltage Vth of the drive transistor TR2. In addition, the period from the time t3 to the time t4 as well as the period from the time t5 to the time t6 are assigned as the periods of compensation for the fluctuations in the threshold voltage Vth of the drive transistor TR2, wherein the voltage differential between the terminals of the signal level hold capacitor C1 is set to the threshold voltage Vth of the drive transistor TR2. Furthermore, three or more of these periods of compensation for fluctuations may be provided as necessary.
The signal level of the signal line SIG is then set to the tone voltage Vsig for the corresponding pixel 3. At a subsequent time t7, the write transistor TR1 is switched on by the write signal WS. This works to counteract the threshold voltage Vth of the transistor TR2 in the pixel 3, and thereby the signal level hold capacitor is set to the tone voltage Vsig. As a result, fluctuations in the luminance of the pixel 3 due to fluctuations in the threshold voltage Vth of the transistor TR2 are prevented.
In the pixel 3 herein, the write transistor TR1 is switched off by the write signal WS at a time t8, occurring after a fixed period of time Tμ passes after the write transistor TR1 is switched on at the time t7. The voltage Vsig of the signal line SIG is meanwhile held by the signal level hold capacitor C1. During this period Tμ, the terminal of the signal level hold capacitor C1 on the side of the OEL element 4 is charged by the driving current of the drive transistor TR2 in accordance with the differential voltage between the terminals of the signal level hold capacitor C1, and thereby the source voltage Vs of the transistor TR1 rises. As indicated in Equation 1, the driving current referred to herein is proportional to the mobility μ, and thus the rate of increase in the source voltage Vs changes during the period Tμ in accordance with the mobility μ of the drive transistor TR2. The differential voltage between the terminals of the signal level hold capacitor C1 is compensated for in the direction of decreasing luminance to the degree that the mobility μ is large. As a result, mobility fluctuation in the drive transistor TR2 of the pixel 3 is compensated for during the period Tμ, while the OEL element 4 is later made to emit light via a bootstrap method, using a driving current in accordance with the differential voltage between the terminals of the signal level hold capacitor C1.
As a result of the configuration in FIG. 5, a pixel circuit is formed using an N-channel transistor, wherein reduced image quality due to fluctuations in the threshold voltage and mobility of the drive transistor TR2 is prevented using a simple circuit configuration.
However, as a result of the configuration shown in FIG. 5, when compensating for fluctuations in the mobility of the drive transistor TR2 during the fixed period Tμ by simply using the tone voltage Vsig, there is a problem in that, fluctuations are over- or under-compensated for depending on the tone voltage Vsig, thereby reducing the image quality.
More specifically, with the configuration in FIG. 5 the following occurs, as illustrated in FIG. 7. When displaying white tones, a relatively high voltage value for the tone voltage Vsig is held compared to that in the case of displaying gray tones. In this case, the rate of increase in the source voltage Vs is higher than that in the case of displaying gray tones. As a result, in this case, fluctuations in the mobility of the drive transistor TR2 are compensated for in a short period of time, as indicated by the period TW. FIG. 7 shows the change in the source voltage Vs for both high-mobility and low-mobility cases, as indicated by lines L3 and L4, respectively.
In contrast, when displaying gray tones, a relatively low voltage value for the tone voltage Vsig is held compared to that in the case of displaying white tones, and thus the rate of increase in the source voltage Vs is lower than that in the case of displaying white tones. As a result, the time period required to compensate for mobility fluctuations in the drive transistor TR2 becomes longer, as indicated by the period TG.
A method for resolving this problem has been devised, wherein during the period Tμ for compensating for mobility fluctuations, the signal level of the signal line SIG is switched from the fixed voltage Vofs to the tone voltage Vsig, with a predetermined intermediate voltage Vofs2 therebetween. This method is shown in FIGS. 8 and 10. Herein, FIG. 8 shows the case wherein a tone voltage Vsig(W) for a white tone is applied, while FIG. 10 shows the case wherein a tone voltage Vsig(B) for a black tone is applied.
When displaying a white tone in this manner, the amount of time T1 required to compensate for mobility fluctuations in the drive transistor TR2 is longer than that of the example in FIG. 5, as indicated by the arrow in FIG. 9. The broken line in FIG. 9 shows the change in the source voltage Vs of the drive transistor TR2 as a result of the configuration in FIG. 5.
In addition, when displaying gray tones, the amount of time T2 required to compensate for mobility fluctuations in the drive transistor TR2 can be reduced to a value smaller than that of the example in FIG. 5, as indicated by the arrow in FIG. 11. The broken line in FIG. 11 shows the change in the source voltage Vs as a result of the configuration in FIG. 5.
Compensating for mobility fluctuations as above by raising the signal level of the signal line SIG from the fixed voltage Vofs to the tone voltage Vsig with a predetermined intermediate voltage Vofs2 therebetween enables mobility fluctuations to be appropriately compensated for by setting this intermediate voltage Vofs2, even in cases wherein there is a variety of different luminance levels. When compensating for mobility via an intermediate voltage Vofs2 in this manner, however, it is necessary to extend the mobility compensation period Tμ so as to be longer than that of the configuration shown in FIG. 5.
However, waveform irregularity of the write signal WS becomes smallest near the input terminal of the scan line SCN in the display unit 2 (as shown in area A in FIG. 12), while waveform irregularity becomes larger as the signal becomes more distant from the input terminal (as shown in area B). As a result, the timing by which the write transistor TR1 is switched on/off varies as the write signal WS grows more distant from the input terminal. Moreover, the period Tμ2, during which mobility is compensated for by using the intermediate voltage Vofs2, becomes shorter with increasing distance from the input terminal. This causes shading to occur in the horizontal direction of the screen.